1. Field of the Invention
The present invention relates generally to an inter-hierarchy synchronizing system and an LSI using this system and, more particularly, to an LSI in which the existing system is actualized based on a hierarchical structure in a semiconductor chip.
2. Description the Prior Art
An LSI having as many as several millions or more of elements is complicated in its configuration and is therefore impossible to design manually. Designing inevitably involves a computer aided design (CAD). In this case, an integrated circuit is constructed by combining predesigned blocked circuits. The typical blocks to be combined are designed by use of gate arrays and standard cells.
FIG. 1 is an internal block diagram showing one example of a conventional LSI employed as a system constituting a large proportion or a part of an applied appliance. As illustrated in FIG. 1, this LSI is constructed in such a way that first through eighth circuit blocks 1-8 are formed in an LSI chip 11. These blocks 1-8 are operated in response to clock signals from an internal 2-phase clock generating part 9 or an external clock input terminal 10. Further, these blocks 1-8 are formed to input and output signals to the exterior of the LSI chip 11 via a bonding pad area 12.
A design of such an LSI involves fractionalizing the system into the first to eight blocks according to their functions and designing logical circuits for the respective blocks by use of gate arrays, etc.. Then, all these blocks 1-8 are connected. Contents of a logical drawing are inputted to a CAD tool. Whether the design is correct or not is verified by performing logical simulation of the whole. A layout, wiring, a prototype production and an improvement of the LSI are conducted based on a result of this verification.
Further, the following method is employed for obtaining a correct and stable operation of the LSI. To be specific, synchronizing clocks supplied from the internal 2-phase clock generating part 9 or the external clock input terminal 10 are delivered to the overall chip. For example, the respective blocks are unified by a single 2-phase clock system such as clocks .PHI.1, .PHI.2. Further, storage circuit parts are constructed of synchronous type circuits to the greatest possible degree. In addition, the essential timing judging and generating parts are operated in synchronism by means of single 2-phase clocks. As a result, control signals are transmitted as if spreading a net between the respective circuit blocks. The respective circuits are thus linked in a firm timing dependent relationship.
As described above, the conventional LSI adopts a so-called absolute synchronism design method, wherein the overall area of the chip is synchronized by using the single 2-phase clock system with respect to logical components such as microprocessors, gate arrays and standard cells in order to stably operate this LSI. Under such circumstances, if timings indicated by the single 2-phase clocks delivered to the overall chip separately arrive at a certain location in chip, this embraces possibility to cause a malfunction of the in-chip circuit system.
This possibility can be seen in the real scene. The method given above can not be applied even with the present CMOS process on the rule or 1.5 .mu.m-1.0 .mu.m in some cases.
Referring to the system of FIG. 1 for example, the interior of the chip is fractionalized into the first to eight blocks 1-8. During this block fractionalizing, there is almost no case where the design is conducted by elaborately analyzing a system request specification. That is, the dominant method is a chip construction method of directly allocating large-scale cells (mega cells) constituting independent high-function blocks of peripheral cores, MPU cores and further a cell library containing known physical dimensions of already-designed ALUs, multiplexers, decoders, register files, flip-flops, ROMs, RAMs, counters, shift registers and primitive gates (NAND, NOR, NOT, etc.).
Accordingly, as explained above, if this absolute synchronism design method is unreasonably applied to a high-speed VLSI, the clock delivery line group is brought into an almost stray state. It is almost impossible to give a consideration in terms of design to relieve this state. Consequently, the probability to cause the malfunction remarkably increases.
For this reason, the clock frequency is decreased in an attempt to obtain reliable operation. As a result, in the case of the LSI constructed on the rule of 1.0 .mu.m, the situation is such that the maximum system operation speed of the entire chip has to be set, though the element switching speed is as high as 300 ps-1 ns, extremely down to 1/50-1/100 of this maximum speed.
It is predicted that the VLSI in the future will adopt a hyperfine technology on the rule of 0.6 .mu.m or under and have several millions to several ten millions of elements for logic and approximately one hundred million of elements for memory. It is also predicted that the chip size will become as large as 10 mm.times.10 mm or more. Besides, the operation frequency is increased up to 30 MHz-100 MHz.
Under such circumstances, a rate of wiring delay time increases as compared with an element delay time. More specifically, the element switching speed is 0.1-0.3 ns, while the wiring delay becomes several ns/mm. For instance, one clock is 10 ns in a clock frequency of 100 MHz, and therefore it may be understood how large the influence of the wiring delay is.
If the LSI chips that have already been put on the commercial line are to be shrunk in size in an attempt to reduce the costs and increase the speed at the present time, the malfunction of the chip is induced. In the majority of cases, the design is forced to be fundamentally reviewed. More naturally, the VLSI takes the intrinsic synchronizing method of clocks in every portion of the chip. Consequently, a large phase difference is forced to occur due to indirect fluctuations in tinting and delivery route.
As explained above, the side effect in terms of timing increases with a larger chip size and a finer process. This aspect will be exemplified with reference to timing charts of FIGS. 2A-2G. As illustrated in FIGS, 2A and 2B, when arriving at the in-system blocks, clocks .PHI..sub.11, .PHI..sub.12 of a clock .PHI.1 and clocks .PHI..sub.21, .PHI..sub.22 of a clock .PHI.2 largely shift in phase as in the case of clocks .PHI..sub.'11, .PHI..sub.'12 of a clock .PHI.'1 and clocks .PHI..sub.'21, .PHI..sub.'22 of a clock .PHI.'2 as shown in FIGS. 2D and 2E.
Consider a circuit shown in FIG. 3 by way of an example of the system operating with such clocks. Data D shown in FIG. 2C is fetched from a first storage circuit 13 shown in FIG. 3. Data D' shown in FIG. 2F is fetched from a second storage circuit 14. It is assumed that an output X illustrated in FIG. 2G is obtained from a combinational circuit/storage circuit 15 to which outputs of the storage circuits 13, 14 are inputted. In this case, it is also assumed that the clocks .PHI.1, .PHI.2 shown in FIGS. 2A and 2B are supplied to the first storage circuit 13; the clocks .PHI.'1 , .PHI.'2 shown in FIGS. 2D and 2E are supplied to the second storage circuit 14; and the clock .PHI.'2 is supplied to the combinational circuit/storage circuit 15. In this instance, there arises a problem when an expected result f (D1, D'1) is not obtained as the output X from the combinational circuit/storage circuit 15, but an incorrect result f (D'1, D2) comes out.
Further, the phase difference derived from a difference in length among the delivery routes of the clock system and a turn-around thereof causes a critical path in every portion of the IC. The advantages of the synchronism type circuit design method are lost. To avoid this situation, there is needed a local time adjustment for queuing till the next safety timing. It follows that this presents a new problem wherein an extra increment in the number of elements is induced, and further the timing can not be broadly predicted. Moreover, this again causes the malfunction due to the shrinkage in size of the chip and the circuit modification that have hitherto been implemented.
Hence, the problems described above are big obstacles in the present scene where ASIC (Application Specific IC) spreads widely in such cases that the designer uses the already-completed LSI as a mega cell by shrinking this LSI and that the LSI design is effected on a larger scale by utilizing a library of mega cells which have already been offered by LSI manufacturers. This situation implies that when constructing the large-scale software, the common variable effective in the small-scale software in turn causes a side effect enough not to actualize a software construction.
As stated above, the conventional LSI does not actually, though the design based on the absolute synchronism system as an essential requirement is adopted, include the method of creating the absolute timing. It is therefore impossible to find out a broad design method capable of predicting a completely operated LSI. The actually designed LSI acquires some reliability to such an extent that an operating possibility remains.